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Description | HIPERFACE DSL® MASTER IP Core for implementation in servo controller, HIPERFACE DSL® is a rapid digital protocol for motor feedback systems that connects servo drives to SICK motor feedback encoders. For detailed information about the protocol, IP Core, and all implementation and testing aspects, please refer to the HIPERFACE DSL® Master Integration Manual (8017595) and the HIPERFACE DSL® Master Safety Integration Manual (8017596) |
Product category | FPGA IP-Core |
Supported programming languages | VHDL |
Version | IP-Core Version 1.07 |
Documentation | HIPERFACE DSL® Master Integration Manual (8017595) HIPERFACE DSL® Master Safety Integration Manual (8017596) |
Supported products | Motor feedback systems rotary HIPERFACE DSL® EDS/EDM35, EKS/EKM36, EES/EEM37, EFS/EFM50 |
Interface | SPI, EMIFA or customer-specific |
Programming language | VHDL |
Required FPGA resources | XILINX: ± 2,400 registers, safety system ± 2,800 registers Altera: ± 3,700 logic elements, safety system ± 4,700 logic elements Lattice: ± 3,900 logic elements, safety system ± 4,500 logic elements |
Supported development environment | XILINX ISE, XILINX Vivado, ALTERA Quartus, Lattice Diamond |
ECl@ss 9.0 | 19200610 |
ECl@ss 10.0 | 19200610 |
ECl@ss 11.0 | 19200610 |
ETIM 5.0 | EC000809 |
ETIM 6.0 | EC000809 |
ETIM 7.0 | EC000809 |
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